Arches Computing Systems develops products and applications based on heterogeneous computing platforms comprising high-performance processors and reconfigurable logic using FPGAs. Key to Arches' technology is the development of communication libraries for these heterogeneous systems. These modules provide application scalability and portability to FPGA-accelerated high-performance computing applications and embedded systems that require a tight coupling between high-performance processors and FPGAs.
Established in 2003, Arches aims to be the technology leader in architectural innovations for heterogenous high-performance computing and embedded systems. The company is based in Toronto, Ontario, Canada.
The Arches-TCP and Arches-UDP stacks are low-latency, FPGA-based networking stacks that allow your FPGA application to communicate using standard networking protocols without incurring the delays associated with standard OS networking stacks. Both stacks achieve 10Gbps sustained line performance and sub-microsecond latency. The TCP stack supports flow control/congestion and allows up to 16 000 simultaneous connections. DHCP, ARP, ICMP, and IGMP modules are included in the libraries.
The Arches-FIX engine is a FPGA-based, low-latency Financial Information eXchange (FIX) engine. It can be configured to run in client or server mode and has default implementations for all FIX Administrative messages. All application-level messages can be offloaded to dedicated logic or an embedded processor directly on the FPGA, or they can be communicated to a server CPU for processing. The Arches-FIX engine supports FIX 4.0 and FIX 4.2 and up to 16 000 simultaneous connections.
The Arches-MPI communication suite targets parallel processes that run on FPGA or FPGA/CPU networks. It consists of software libraries and FPGA IP and enables the distribution of tasks across a collection of server CPUs, embedded processors, and FPGA-based computing engines. Since the communication interface is standard MPI, development will be familiar to many programmers and can easily evolve from software-only to a software/hardware hybrid to take advantage of FPGA acceleration.
Many existing applications are candidates for hardware acceleration, where the computational bottlenecks are identified and re-implemented in dedicated logic on a FPGA.
We will first profile your application to identify the expected speedup obtained by moving some or all of your application to hardware.
Next, we will re-implement those modules in hardware and provide all of the necessary peripheral logic so the only observable difference is the application acceleration.
Arches Computing Systems also provides a complete system design service to design and implement your application directly on a FPGA, or in a heterogeneous CPU/FPGA environment.
Starting with a requirements document, Arches will design an architecture to best utilize the massive parallelization available in dedicated hardware.
After completing the architecture design, Arches will implement the design on a FPGA and work with you to ensure compliance with the design specification.
Kwong Ho is responsible for the overall operations of the company. He works with customers and suppliers to establish strategic partnerships. Prior to Arches Computing Systems, Kwong was the President and CEO of Digital V6 Corp. and the VP of Operations at Concord Idea Corp. where the company was recognized in Deloitte & Touche's Canadian FAST50. Kwong has extensive technical marketing experience as VP Marketing at ASPRO Technologies and Field Applications Engineer for various companies in the electronics industry. Kwong earned his B.A.Sc.(Engineering Science) and M.B.A.(Rotman) from the University of Toronto, and J.D. from the University of Western Ontario.
Dr. Chow is a Professor in the Department of Electrical and Computer Engineering at the University of Toronto where his current research is focused on heterogenous architectures using multi-FPGA systems and high-performance processors. He has worked on commercial ASIC designs and managed a design and verification team of over 30 people at AcceLight Networks, where he was a co-founder. He also has experience in the design and implementation of sophisticated CAD flows. Dr. Chow is currently on the Board of Directors at CMC Microsystems.
Dr. Madill is the lead architect at Arches Computing Systems. He has many years experience in the development of high-performance computing architectures, both in software and in hardware. His expertise ranges from ultra-low latency financial application to massively parallel simulation of biomolecular systems. Dr. Madill earned a B.Sc (Honours) in Computer Science and Biochemistry from Queen's University and a Ph.D in Biochemistry from the University of Toronto. Prior to completing his Ph.D, he gained extensive development experience at Cognos, Molecular Mining, and The Hospital for Sick Children.
Jimmy Lin is a hardware engineer at Arches Computing Systems. He gained extensive FPGA design experience through his B.Eng. at Shanghai Jiao Tong University and his MASc at the University of Toronto. Before joining Arches, Jimmy was a member of the SDAccel Development Enviroment team at the Xilinx San Jose research labs. He currently specializes in the development of IP cores and low-latency networking stacks.
info @ archescomputing.com
545 King St W, Toronto, ON. M5V 1M1