High-Performance FPGA IP Cores
These IP cores are available for integration into existing FPGA designs.
The ArchES TCP/IP Stack is a high-performance suite of networking cores that connect FPGA applications to TCP networks. It executes on 10, 25, 40, 50, and 100G networks and can be optimized for latency or throughput. It supports up to 16000 simultaneous sessions, and can be configured to operate in cut-through mode using both on-chip and external memory.
The ArchES UDP Stack is a high-performance suite of networking cores that connect FPGA applications to UDP networks. Like the ArchES TCP Stack, the UDP stack runs natively on 10, 25, 40, 50, or 100G networks and supports cut-through operation.
The ArchES FIX Engine is a high-performance Financial Information eXchange engine for connecting FPGA applications to other FIX endpoints. It is designed for tight coupling with the ArchES TCP stack and operates on 10-100G TCP networks. The FIX Engine can be configured to operate as a FIX Initiator or Acceptor. In Acceptor mode, the FIX Engine supports up to 16000 simultaneous sessions. External database logging, drop-copies, session monitoring, and session control are all natively supported. Many different FIX versions are supported, as are completely custom FIX dictionaries.
Level II Market Data Feed Handler
The ArchES Level II Market Data Feed Handler is a high-performance FPGA core that enables extremely low-latency access to market-data feeds. By embedding the Feed Handling directly on the same device as your algo (trading strategy, risk monitor, order router, etc.), your FPGA applications have access to the performance advantage of hardware feed handling without the latency penalties of external feed handlers.